SEOUL, South Korea-- Dongbu Electronics today announced that it has collaborated with Cadence Design Systems, Inc. (NASDAQ:CDNS) to jointly develop an RTL-to-GDSII Reference Flow, the DBE 130.2 Reference Flow. The flow, based on the Cadence(R) Encounter(R) Digital IC design platform, provides a proven solution for volume production of chips at the 130-nanometer node. In addition, Dongbu has joined the Cadence Foundry Program as an Advocate Partner to enhance delivery of combined solutions to customers.
"Our collaboration with Cadence has been very productive, and we are quite happy with the results from the new Reference Flow," said Dr. Jae Song, Executive Vice President, Dongbu Electronics. "We look forward to leveraging fully our participation in the Cadence Foundry Program to enable more advanced solutions for our customers in the coming months."
The new Reference Flow is a complete front to back solution, including RTL and gate-level simulation and equivalence checking. It includes power optimization through clock-gating insertion, as well as proven prevention of signal-integrity problems through analysis and repair.
The Cadence Foundry Program builds alliances with foundries to create and deliver comprehensive design kits and reference flows for mainstream and advanced process technologies. Cadence collaborates with its foundry partners to help ensure that engineers using Cadence technology have a smooth and efficient path from design through physical implementation.
"Cadence is collaborating with all leading foundries to provide a comprehensive set of options to design engineers," said Jan Willis, senior vice president, Industry Alliances, at Cadence. "The successful collaboration with Dongbu Electronics sets a milestone for Cadence in Korea, and another example of how leading-edge Cadence solutions provide a viable way to working silicon for customers world-wide." The Reference Flow incorporates the Cadence SoC Encounter(R) System, Encounter RTL Compiler global synthesis, VoltageStorm(R) power grid verification, Encounter Conformal(R) verification technologies, Cadence QRC Extraction, and Assura(TM) DRC/LVS physical verification. Cadence and Dongbu Electronics also are jointly developing Process Design Kits (PDKs) for several Dongbu Electronics process technologies. These PDKs provide the crucial link between foundry process data and the tools used in custom, analog, and mixed-signal design methodologies. Dongbu Electronics uses the Cadence Virtuoso(R) custom design platform and these PDKs to develop physical IP.
About Dongbu Electronics
Dongbu Electronics provides world-class CMOS processing for system-on-chip solutions that integrate advanced logic, analog, and mixed-signal technologies. As a "Specialty Solution Partner" in high-growth markets, such as those represented by mobile handsets and flat-panel displays, Dongbu adds high value with specialized processing for CMOS Image Sensor (CIS), High Voltage, Embedded Flash, and LCD Driver IC (LDI) functions. Dongbu"s collaborate-and-thrive approach is evident across the entire manufacturing spectrum including prototype development/verification, packaging/module development, complete turnkey solutions, and accelerating time to volume production. The company"s stock is publicly traded under 001830 on the Korea Stock Exchange. For more information, click on http://www.dsemi.com. Cadence, the Cadence logo, Encounter, VoltageStorm, and Conformal are registered trademarks of Cadence Design Systems in the United States and other countries. Assura is a trademark of Cadence Design Systems. All other trademarks are the property of their respective owners. ======================================================================== By Dylan McGrath SAN FRANCISCO ? South Korean foundry Dongbu Electronics said Wednesday (May 24) it has collaborated with EDA market leader Cadence Design Systems Inc. to jointly develop an RTL-to-GDSII reference flow, dubbed the DBE 130.2 Reference Flow.
The flow, based on the Cadence Encounter Digital IC design platform, is intended for volume production of chips at the 130-nanometer node, Dongbu (Seoul, South Korea) said. The company said it has joined the Cadence Foundry Program as an advocate partner.
"Our collaboration with Cadence has been very productive, and we are quite happy with the results from the new reference flow," said Jae Song, Dongbu executive vice president, in a prepared statement.
Dongbu describes the new reference flows as "a complete front to back solution," including RTL and gate-level simulation and equivalence checking. The flow includes power optimization through clock-gating insertion, as well as proven prevention of signal-integrity problems through analysis and repair, the company said.
Dongbu said it is also jointly developing with Cadence (San Jose, Calif.) process design kits (PDKs) for several Dongbu process technologies. These PDKs provide a link between foundry process data and the tools used in custom, analog and mixed-signal design methodologies, Dongbu said.
The reference flow incorporates: The Cadence SoC Encounter System Encounter RTL Compiler global synthesis VoltageStorm power grid verification Encounter Conformal verification technologies Cadence QRC Extraction Assura DRC/LVS physical verification
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